1. Field of the Invention
This invention relates generally to methods of testing integrated circuit (IC) devices, and more particularly, to a method of testing IC devices to determine whether a low impedance path exists between input/output (I/O) pins and IC ground.
2. Description of the Prior Art
It is well known that a four-layer sandwich of doped material NPNP, forms a silicon-controlled rectifier (SCR). Once an SCR is xe2x80x9cfiredxe2x80x9d (switched to its xe2x80x98ONxe2x80x99 conducting state), it continues to conduct until its gate signal is removed. The SCR is sometimes undesirable for certain applications, since inadvertent firing of an SCR will usually result in excessive current flow. This excessive current flow can result in destructive failure of an integrated circuit that employs an SCR.
CMOS devices always have parasitic SCR structures. The firing of an SCR is termed latch-up in CMOS circuits. A CMOS designer must therefore be certain that latch-up cannot occur in any CMOS design, i.e., a malfunction of a CMOS integrated circuit caused by firing a parasitic PNPN structure. Latch-up, as used herein, means a state in which a low impedance path results from an overstress that triggers a parasitic SCR structure, and that persists after removal or cessation of the trigger condition.
Testing for latch-up during device testing is important to isolating devices with latch-up problems. Conventional latch-up test techniques cannot however, detect a potential low impedance path between I/O(s) and GND(s) where the low impedance path is caused by a parasitic SCR (micro-latch-up), since the anode of the SCR is placed in the I/O path.
In view of the foregoing, it would be desirable and advantageous in the art to provide a reliable method of testing an integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up.
The present invention is directed to a reliable method of testing an integrated circuit device having a low-impedance path between I/O pin(s) and GND for potential micro-latch-up.
In one aspect of the invention, a test method is provided to detect a low impedance path between integrated circuit device I/O pin(s) and GND(s), to increase device reliability during test and/or qualification processing.
In another aspect of the invention, a test method is provided to detect a low impedance path between integrated circuit device I/O pin(s) and GND(s) caused by a parasitic SCR.
In still another aspect of the invention, a test method is provided to detect a low impedance path between integrated circuit device I/O pin(s) and GNS(s) that are not detectable using conventional latch-up detection test methods.